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MC100EL39 5V ECL /2/4, /4/6 Clock Generation Chip
The MC100EL39 is a low skew /2/4, /4/6 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open. The common enable (EN) is synchronous so that the internal dividers will only be enabled/disabled when the internal clock is already in the LOW state. This avoids any chance of generating a runt clock pulse on the internal clock when the device is enabled/disabled as can happen with an asynchronous control. An internal runt pulse could lead to losing synchronization between the internal divider stages. The internal enable flip-flop is clocked on the falling edge of the input clock, therefore, all associated specification limits are referenced to the negative edge of the clock input. Upon startup, the internal flip-flops will attain a random state; therefore, for systems which utilize multiple EL39s, the Master Reset (MR) input must be asserted to ensure synchronization. For systems which only use one EL39, the MR pin need not be exercised as the internal divider design ensures synchronization between the /2/4 and the /4/6 outputs of a single device.
Features
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SO-20 WB DW SUFFIX CASE 751D
MARKING DIAGRAM*
20 100EL39 AWLYYWWG
* * * * * * * * * * * * * *
50 ps Output-to-Output Skew Synchronous Enable/Disable Master Reset for Synchronization ESD Protection: Human Body Model; > 2 kV, Machine Model; > 100 V The 100 Series Contains Temperature Compensation PECL Mode Operating Range: VCC = 4.2 V to 5.7 V with VEE = 0 V NECL Mode Operating Range: VCC = 0 V with VEE = -4.2 V to -5.7 V Internal Input Pulldown Resistors on EN, MR, CLK(s), and DIVSEL(s) Q Output will Default LOW with Inputs Open or at VEE Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test Moisture Sensitivity Level 1 For Additional Information, see Application Note AND8003/D Flammability Rating: UL 94 V-0 @ 0.125 in, Oxygen Index 28 to 34 Transistor Count = 419 devices Pb-Free Packages are Available*
1 A WL YY WW G = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package
*For additional marking information, refer to Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet.
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
(c) Semiconductor Components Industries, LLC, 2006
November, 2006 - Rev. 6
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Publication Order Number: MC100EL39/D
MC100EL39
VCC 20 Q0 19 Q0 18 Q1 17 Q1 16 Q2 15 Q2 14 Q3 13 Q3 12 VEE 11
Table 1. PIN DESCRIPTION
Pin CLK, CLK EN MR Q0, Q0; Q1, Q1 Q2, Q2; Q3, Q3 DIVSELa, DIVSELb VBB VCC VEE NC Function ECL Diff Clock Inputs ECL Sync Enable ECL Master Reset ECL Diff /2/4 Outputs ECL Diff /4/6 Outputs ECL Frequency Select Input ECL Frequency Select Input Reference Voltage Output Positive Supply Negative Supply No Connect
1
2
3 DIVSELb
4
5
6
7 MR
8 VCC
9 NC
10 DIVSELa
VCC EN
CLK CLK VBB
NOTE: All VCC pins are tied together on the die. Warning: All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation.
Figure 1. Pinout: SOIC-20 (Top View) Table 2. FUNCTION TABLE
DIVSELa Q0 CLK CLK P2/4 R Q0 Q1 Q1 Q2 P4/6 R MR DIVSELb Q2 Q3 Q3 Function Divide Hold Q0-3 Reset Q0-3 CLK* Z ZZ X EN* L H X MR* L L H
Z = Low-to-High Transition ZZ = High-to-Low Transition *Pin will default low when left open.
EN
DIVSELa** 0 1 DIVSELb** 0 1 **Pin will default low when left open.
Q0, Q1 Outputs Divide by 2 Divide by 4 Q2, Q3 Outputs Divide by 4 Divide by 6
Figure 2. Logic Diagram
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MC100EL39
Table 3. MAXIMUM RATINGS
Symbol VCC VEE VI Iout IBB TA Tstg qJA qJC Tsol Parameter PECL Mode Power Supply NECL Mode Power Supply PECL Mode Input Voltage NECL Mode Input Voltage Output Current VBB Sink/Source Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction-to-Ambient) Thermal Resistance (Junction-to-Case) Wave Solder Pb Pb-Free 0 lfpm 500 lfpm Standard Board <2 to 3 sec @ 248C <2 to 3 sec @ 260C SOIC-20 SOIC-20 SOIC-20 Condition 1 VEE = 0 V VCC = 0 V VEE = 0 V VCC = 0 V Continuous Surge VI VCC VI VEE Condition 2 Rating 8 -8 6 -6 50 100 0.5 -40 to +85 -65 to +150 90 60 30 to 35 265 265 Unit V V V V mA mA mA C C C/W C/W C/W C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
Table 4. 100EL SERIES PECL DC CHARACTERISTICS VCC = 5.0 V; VEE = 0.0 V (Note 1)
-40C Symbol IEE VOH VOL VIH VIL VBB VIHCMR Characteristic Power Supply Current Output HIGH Voltage (Note 2) Output LOW Voltage (Note 2) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Output Voltage Reference Common Mode Range (Differential) (Note 3) VPP < 500 mV VPP w 500 mV Input HIGH Current Input LOW Current 0.5 3915 3170 3835 3190 3.62 1.3 1.5 Min Typ 50 3995 3305 Max 59 4120 3445 4120 3525 3.74 4.6 4.6 150 0.5 3975 3190 3835 3190 3.62 1.2 1.4 Min 25C Typ 50 4045 3295 Max 59 4120 3380 4120 3525 3.74 4.6 4.6 150 0.5 3975 3190 3835 3190 3.62 1.2 1.4 Min 85C Typ 54 4050 3295 Max 61 4120 3380 4120 3525 3.74 4.6 4.6 150 Unit mA mV mV mV mV V V
IIH IIL
mA mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 1. Input and output parameters vary 1:1 with VCC. VEE can vary +0.8 V / -0.5 V. 2. Outputs are terminated through a 50 W resistor to VCC - 2.0 V. 3. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between VPPmin and 1.0 V.
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MC100EL39
Table 5. 100EL SERIES NECL DC CHARACTERISTICS VCC = 0.0 V; VEE = -5.0 V (Note 4)
-40C Symbol IEE VOH VOL VIH VIL VBB VIHCMR Characteristic Power Supply Current Output HIGH Voltage (Note 5) Output LOW Voltage (Note 5) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Output Voltage Reference Common Mode Range (Differential) (Note 6) VPP < 500 mV VPP 500 mV Input HIGH Current Input LOW Current 0.5 -1085 -1830 -1165 -1810 -1.38 -3.7 -3.5 Min Typ 50 -1005 -1695 Max 59 -880 -1555 -880 -1475 -1.26 -0.4 -0.4 150 0.5 -1025 -1810 -1165 -1810 -1.38 -3.8 -3.6 Min 25C Typ 50 -955 -1705 Max 59 -880 -1620 -880 -1475 -1.26 -0.4 -0.4 150 0.5 -1025 -1810 -1165 -1810 -1.38 -3.8 -3.6 Min 85C Typ 54 -955 -1705 Max 61 -880 -1620 -880 -1475 -1.26 -0.4 -0.4 150 mA mA Unit mA mV mV mV mV V V
IIH IIL
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 4. Input and output parameters vary 1:1 with VCC. VEE can vary +0.8 V / -0.5 V. 5. Outputs are terminated through a 50 W resistor to VCC - 2.0 V. 6. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between VPPmin and 1.0 V.
Table 6. AC CHARACTERISTICS VCC = 5.0 V; VEE = 0.0 V or VCC = 0.0 V; VEE = -5.0 V (Note 7)
-40C Symbol fMAX tPLH tPHL Characteristic Maximum Toggle Frequency Propagation Delay to Output CLK Q (Differential) CLK Q (Single-Ended) MR Q Within-Device Skew (Note 8) Q0 - Q3 Part-to-Part Q0 - Q3 (Diff) Random CLOCK Jitter (RMS) @ 1.0 GHz Setup Time Hold Time Input Swing (Note 9) Reset Recovery Time Minimum Pulse Width CLK MR 500 700 280 550 EN CLK DIVSEL CLK CLK EN CLK Div_Sel 250 400 100 150 150 1000 100 500 700 280 550 2.0 Min 1.0 850 850 600 1150 1150 900 50 200 3.0 250 400 100 150 150 1000 100 500 700 280 550 2.0 Typ Max Min 1.0 900 900 610 1200 1200 910 50 200 3.0 250 400 100 150 150 1000 100 2.0 25C Typ Max Min 1.0 950 950 630 1250 1250 930 50 200 3.0 85C Typ Max Unit GHz ps
tSKEW tJITTER tS tH VPP tRR tPW tr, tf
ps ps ps ps mV ps ps ps
Output Rise/Fall Times Q (20% - 80%)
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 7. VEE can vary +0.8 V / -0.5 V. Outputs are terminated through 50 W resistor to VCC - 2.0 V. 8. Skew is measured between outputs under identical transitions. 9. VPP(min) is minimum input swing for which AC parameters guaranteed. The device has a DC gain of 40.
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MC100EL39
tRR MR CLK Q (P2) Q (P4) Q (P6)
Figure 3. Timing Diagram
Q Driver Device Q
Zo = 50 W
D Receiver Device
Zo = 50 W 50 W 50 W
D
VTT VTT = VCC - 2.0 V
Figure 4. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D - Termination of ECL Logic Devices.)
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MC100EL39
ORDERING INFORMATION
Device MC100EL39DW MC100EL39DWG MC100EL39DWR2 MC100EL39DWR2G Package SOIC-20 SOIC-20 (Pb-Free) SOIC-20 SOIC-20 (Pb-Free) Package 38 Units / Rail 38 Units / Rail 1000 / Tape & Reel 1000 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D AN1406/D AN1503/D AN1504/D AN1568/D AN1672/D AND8001/D AND8002/D AND8020/D AND8066/D AND8090/D - ECL Clock Distribution Techniques - Designing with PECL (ECL at +5.0 V) - ECLinPS I/O SPiCE Modeling Kit - Metastability and the ECLinPS Family - Interfacing Between LVDS and ECL - The ECL Translator Guide - Odd Number Counters Design - Marking and Date Codes - Termination of ECL Logic Devices - Interfacing with ECLinPS - AC Characteristics of ECL Devices
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MC100EL39
PACKAGE DIMENSIONS
SO-20 WB DW SUFFIX CASE 751D-05 ISSUE G
D
A
11 X 45 _
q
NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A A1 B C D E e H h L q MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 12.65 12.95 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_
H
M
B
M
20
10X
0.25
E
1 10
20X
B 0.25
M
B TA
S
B
S
A e
SEATING PLANE
h
18X
A1
T
C
ECLinPS are registered trademarks of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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L
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MC100EL91/D

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